The Advantages of Latch-Based Design Under Process Variation

Latch-based design may offer power and area savings, but its theoretical performance is no better than that of register-based design after clock scheduling is applied. Under the traditional deterministic timing model, the optimal period in both latchand register-based designs is limited by the maximum mean delay of any cycle in the circuit. However, when process variation is considered, latch-based design is often dramatically more variationtolerant, resulting in a better yield and/or allowing a more aggressive clocking than the equivalent design with registers. This effect can not be observed using traditional deterministic timing analysis and requires a probabilistic timing model to quantify. We analyze several benchmark circuits, and demonstrate that manufacturing a latch-based design will result in 4 times fewer failures than the equivalent design using registers. Finally, we consider of the problem of how to schedule the clocks of latches to further maximize the yield.